Wednesday, February 13, 2008. CDC - Clock Domain Crossing guidelines. A good article on CDC guidelines. Understanding Clock Domain Crossing Issues. Asynchronous signals in a synchronous world. Tuesday, January 29, 2008. Flip Flops and Register timings. The two important timings of a flip flop are. Divide by 3 first and add the negedge flop in series to make divide by 3.

This Blog is created for Basic VLSI Interview Questions. This content is purely VLSI Basics. Wednesday, 30 April 2014. Here I am going to discuss about Tie Cells Insertion. Before going to know about Tie Cells Insertion, We have to know what Tie Cells are. Why Tie cells are inserted? In lower technology nodes the gate ox.

Wednesday, September 7, 2011. VCD File In Power Analysis. VCD Stands for Value Change Dump, VCD file is used for verilog simulation and power analysis. VCD file is an ASCII format file include waveform information, this file is used by Verilog simulators. VCD file fromat is defined by IEEE Standard 1364. Tuesday, July 5, 2011.

VLSI Concepts was founded in 1995 by Dr. Dr Hepler began his career as a Member of Technical Staff in the Processor Design laboratory of Bell Laboratories where he helped design high reliability processors used in electronic switching systems. From there he moved to the Space Systems Division of General Electric and then to Commodore Business Machines where he developed chips for next generation Amiga machines.

Tuesday, December 24, 2013. Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Consider a hierarchical design where we have.